One of the primary steps in the fabrication of modern semiconductor devices is the formation of an insulating layer, such as a silicon oxide layer, on a substrate or wafer. Such insulating layers are used in the formation many different features in an integrated circuit including shallow trench isolation (STI) structures and premetal dielectric (PMD) layers among others. In both STI and PMD applications, the gapfill capability of the insulating layer is an important physical characteristic.
As is well known, one method for depositing silicon oxide and other insulating layers for STI and PMD applications is by chemical vapor deposition (CVD). In a conventional thermal CVD process, reactive gases are supplied to the substrate surface where heat-induced chemical reactions take place to form the desired film. In a conventional plasma CVD process, a controlled plasma is formed using, for example, radio frequency (RF) energy or microwave energy to decompose and/or energize reactive species in reactant gases to produce the desired film. Because of the importance of completely filling gaps, such as trenches in STI applications and gaps between adjacent raised surfaces in PMD applications, with the insulating film, such CVD operations, whether plasma and thermal, are often performed at substrate temperatures above 500° C.
Unwanted deposition on areas such as the walls of the processing chamber occurs during such CVD processes. As is known in the industry, it is common to remove the unwanted deposition material that builds up on the interior of chamber walls with an in situ chamber clean operation. Common chamber cleaning techniques include the use of an etchant gas, such as nitrogen trifluoride (NF3), to remove the deposited material from the chamber walls and other areas. In some processes, the etchant gas is introduced into the chamber and a plasma is formed so that the etchant gas reacts with and removes the deposited material from the chamber walls. Such cleaning procedures are commonly performed between deposition steps for every wafer or every n wafers.
Many of the commercially available CVD chambers include aluminum, aluminum oxide and/or aluminum nitride components including chamber liners, substrate heater/pedestals and chamber walls among others. One potential problem in using NF3 or other fluorine-including etchant gases for cleaning unwanted deposits from such aluminum or aluminum oxide chamber parts after a high temperature deposition process is that active fluorine species from the etchant gas may react with the aluminum resulting in the formation of AlO:F and/or AlFx films at the surface of the respective chamber parts. These films have relatively high vapor pressures and relatively low sublimation temperatures (e.g., the sublimation temperature of aluminum fluoride is approximately 600° C.) and can attain thicknesses of several hundred micrometers when conditions for self-passivation are not met. If a particular ceramic component (e.g., heater, electrostatic chuck, cover plate, etc.) is used above the sublimation temperature, the outer surface of the component is consumed during the process in which the AlO:F or AlFx film is formed. Furthermore, it has been observed, that under ion bombardment, an AlF film can be sputtered, even at temperatures less than 400° C. This phenomenon may result in recondensation of the byproducts on colder components (e.g., showerheads and chamber liners) and may lead to process drift and particle contamination in some substrate processing chambers.
One method of preventing such AlO:F and/or AlFx formation is to cool the chamber after the high temperature deposition process and prior to the cleaning process. For example, AlFx typically forms at 480° C. so cooling all the chamber components to a temperature significantly below 480° C. prior to the cleaning process should prevent AlFx formation. Cooling the chamber after the deposition process takes time, however, and also requires that the chamber be reheated back to an appropriate deposition temperature after the cleaning step adversely affecting wafer throughput. Accordingly, it can be appreciated that other techniques are desirable.